Re: [computer-go] question regarding Hydra Chess PC computer

["chrilly" <chrilly@xxxxxxxx>]

>
>
>At 20:19 25-10-2004 -0400, you wrote:
>>Just because a block of hardware appears on the silicon repeated 361 times
>>(or whatever), doesn't mean you need to write that VHDL or Verilog module
>>361 times.  You write something once and instantiate it multiple times,
>>connecting to to different wires.  Similar to writing a function and
calling
>>it from different places.  All hardware people know this.  I expect that
>>this was just lost in the conversation between you and the VHDL guy.
>
>You sure that can get evaluated in parallel and that you told that to
>Chrilly too?
>
According to Peter Alfke - an FPGA-pioneer at XiLinx - is Hydra  one of the
most complex FPGA-Design he knows of.
One can therefor assume that the programmer of this design has at least some
beginners knowledge of hardware-design.
The point mentioned above is is usually chapter 2 in an "HDL for Dummies"
book.

>Note that in some hardware groups when i told Hydra runs about 33Mhz, the
>hardware guys had to laugh loud for too and called it 'years 80 hardware'
>and they gave some links to 400Mhz programmable chips.
>
The Virtex-I we are using is indeed somewhat outdated. But even on a state
of the art FPGA it is only 60MHz.
Peter Alfke did not lough about our figures but donated a few high-end chips
for doing other FPGA-research.
Seems to be the type of Bob-Hyatt-experts which are everywhere on the net.

Chrilly


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