Re: [computer-go] question regarding Hydra Chess PC computer

[Vincent Diepeveen <diep@xxxxxxxxx>]

At 10:10 26-10-2004 +0100, chrilly wrote:
>>
>>
>>At 20:19 25-10-2004 -0400, you wrote:
>>>Just because a block of hardware appears on the silicon repeated 361 times
>>>(or whatever), doesn't mean you need to write that VHDL or Verilog module
>>>361 times.  You write something once and instantiate it multiple times,
>>>connecting to to different wires.  Similar to writing a function and
>calling
>>>it from different places.  All hardware people know this.  I expect that
>>>this was just lost in the conversation between you and the VHDL guy.
>>
>>You sure that can get evaluated in parallel and that you told that to
>>Chrilly too?
>>
>According to Peter Alfke - an FPGA-pioneer at XiLinx - is Hydra  one of the
>most complex FPGA-Design he knows of.

That's very nice from him to say, but not exactly true.

Entire designs get simulated in FPGA and in the big 'companies' where so
many thousands people work, FPGA gets used to make very complex programs,
and they sure aren't shouting around what they're doing. It all gets done
without betraying to 'competitors' their secrets.

It is better to say that nowadays more and more gets done in software,
because of the big gap between FPGA and cheap processing power.

Also encryption/decryption/factorization, which can be done excellent in
FPGA, can of course also be done on general purpose clusters.

Dutch government just ordered a big supercomputer 12288 processors from IBM
with i guess power5+ processors inside. 6 racks of 2048 processors.

This machine is shared with germany and denmark to run at a few processors
some infrared x-files simulation software. It gets installed at Dwingeloo.
No organisation i know has access to it and that chip is very bad for chess
if i look to the crafty specint2000 scores at power5.

>One can therefor assume that the programmer of this design has at least some
>beginners knowledge of hardware-design.

Chrilly, where everyone doubted Hsu, no one doubts your chessprogramming
skills. Hydra is a very strong program, which at 16 processors is just very
strong. 

Of course you know my opinion that there is no difference between running
it in fpga or in software, actually at 16 cpu's with myrinet i'm sure you
could get more out of it because you don't lose quality. 

The quality of the program is not in dispute.

You use nullmove, search deep, and have a very well tuned evaluation function.

Perhaps you would even get in top3 of worldchampionship.

I'm sure it's a lot stronger than Fritz & Crafty which ended 4th and 5th
there in 2004.

Those also ran at big hardware. Quad opterons.

Yet you have 16 processors and perhaps soon even 1024.

In 2004 the world champs was in Israel. It was a consequent act from the
Sheikh to follow his governments advice; which officially is in state of
war with Israel and also doesn't allow anyone who ever travelled to Israel
(stamp in passport), to enter the UAE.

>The point mentioned above is is usually chapter 2 in an "HDL for Dummies"
>book.

How big is your source code and how much have you written out instead of
use great sophisticated things?

>>Note that in some hardware groups when i told Hydra runs about 33Mhz, the
>>hardware guys had to laugh loud for too and called it 'years 80 hardware'
>>and they gave some links to 400Mhz programmable chips.
>>
>The Virtex-I we are using is indeed somewhat outdated. But even on a state
>of the art FPGA it is only 60MHz.
>Peter Alfke did not lough about our figures but donated a few high-end chips
>for doing other FPGA-research.
>Seems to be the type of Bob-Hyatt-experts which are everywhere on the net.

You can print for 50 euro a chip a 1000 chips or so, no problem. 
At about 400Mhz.

The Sheikh told me he wanted to build a 1024 processor machine, sell it to
UAE government, and just use it now and then to run Hydra at it.

Of course chips in range 400Mhz-500Mhz are a lot faster then.

Whether you can also hit 600Mhz with it, i'm no expert there.

It is very wise to not overclock things at clusters.

Your current PC cluster with network cards, probably will not like it when
at every machine the PCI bus gets overclocked :)

Making a chess FPGA chip in order to then run at around 33Mhz is of course
pathetic, when the only advantage FPGA has for that factor 10 times bigger
effort than a software program costs, that it can run faster in fpga than
software when you print chips of around 400-600Mhz or above.

That's what professional 'companies' use FPGA for.

Crafty gets single cpu at an opteron which already isn't the fastest
opteron anymore, a speed of 2.2 million nps.

You hardly get that in hardware meanwhile you're about 5 times less
efficient in hardware.

Diep uses everywhere hashtables and just storing qsearch in hashtables
boosts the TIME 20% faster (apart from a 20% slowdown in nodes a second
thanks to that which effectively means the profit is more like 40%).

Let alone the last 3 ply.

>Chrilly
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