> >Someone (can't remember who) makes simulators that use an array of FPGAs to >simulate your ASIC design. Way faster than software, but still slow. > At the beginning of the project I visited MIT (unfortunately Don Dailey was out) and they had such a simulator. >100 FPGAs. Besides the Powerball-detail Hydra is a combined hardware-software system. There is no straightforeward way to combine/interface these 2 systems. A more realistic way would be to develop first an FPGA and to convert then to ASIC. The problem with this approach is, that the ASIC design reflects then also the limitations of the FPGA-architecture. Competitive ASICs structures - e.g. 130 nanometer - masks are also too expensive for a game playing program. I think the more realistic way is to wait till reasonable sized FPGAs are below 50$. > Can you describe your >architecture? > See enclosed paper. Chrilly
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