Re: [computer-go] Computer Go hardware

>use the FPGAs. FPGA suffers some difficulties. First, the core frequency of today's FPGA is about 500 - 600 MHz at the best which is 6 times lower than the speed of >the available CPU in the PC. It means a 6 fold increase in speed only makes it equivalent to a PC. Thus, a big break through in speed is difficult from the FPGA. The >second difficulty is the complexicity involved. A designer not only need to write the Go program, he need to design the computer at the same time. Even if the FPGA can >handle the complexicity.

500-600MHz is much too high. My FPGA-Chess programm Hydra runs - at a somewhat outdated FPGA - with 30MHz. Depends of course also on the design, but 100MHz is already quite fast. The 500-600 MHz vendors mention are marketing MHz. Same holds for "Multi-million-gates".

If one puts a conventional chess programm 1:1 into a FPGA, one gets about the performance of a 466/33MHz. The point is that one has to transform the algorithm completly. E.g. Hydra needs 9 clock-cycles for one position. On an INTEL it would be about 40.000 instructions. Actually one can not compare it. Some things are very efficient in hardware (e.g. calculating all the attacked squares), some are more efficient in software (e.g. special endgame knowledge). One has therefore to write a different evaluation function. The Hydra evaluation and that of my former conventional programm Nimzo have nothing in common.

The bottleneck is the PCI-bus. A faster bus like PCI-X is fine, but does not change the situation. The bus is always in comparision to the CPU "infinetly" slow. One has to implement a full programm including search into the FPGA. In case of Hydra the first N-3 plies are done in software, the last 3-Plies+Quiesence in Hardware.

All other ways of interfacing are simply not practical. A small revision of the motherboard and nothing works any more. It is much too expensive and cumbersome to design each time a new card.

Technically the best way is to combine fine- and coarse parallelism like we do it in Hydra. A cluster connected with very fast communication cards (e.g Myrinet) plus an FPGA "coprocessor" per CPU.

This Go machine would be - like Hydra - something very exquisite. Even a single-processor card is currently too expensive for the mass-market. XiLinx is announcing since some time, that it will produce very cheap and powerfull FPGAs. So far this is only vapourware (there is generally a high degree of vapourware in the FPGA-business).

The Hydra team has the knowledge to programm such a hardware combination (we have also the hardware). We have no Go-programming knowledge, but the current approaches are anyway of little help for such a machine. One would have to develop new algorithms/heuristics. It is my goal to build the first Dan-level Go programm once the chess question is "solved" (next year). Actually the mid term (5-10 years) goal is to build a Go-program which is as strong as the current chess programs. It should beat the strongest Dans under tournament conditions.

The main problem is - like always - money. I have to convince the other team members and especially the Hydra-sponsor that Go is interesting. So far the reaction is: "just another strange game".

Chrilly