Re: [computer-go] Hardware-Instruction.

["chrilly" <chrilly@xxxxxxxx>]

>
>I don't have a good feeling for how much logic one can cram into one of
>today's FPGAs, so this might not be possible.
>
If money does not count, todays FPGAs are very large. XiLinx gives some
numbers like up to 8 Million gates. But this are marketing-fantasy-numbers.
It is in my oponion difficult to compare. But e.g. in the Virtex-Pro 100 I
have currently I could place 3 Hydra cores (There are even 2 Power-PC-cores
available, but I do not know what to do with them).

> But, if you have a
>sufficiently parallel state representation, this could be done all in
>combinational logic and then pipelined at will to meet the clock.
I think this gets too complex and complicated.
My intention was/is a Cellular Automata like representation. Each
intersection knows just the states of the neighbour-intersections. This
would fit in a relative small FPGA (or one could place several cores in a
big one). But with this design counting e.g. liberties of a string or even
the length of a string is nasty. But it would e.g. be perfect for
calculating influence.
Note: One avoids usually in hardware incremental calculations. Marking what
has been already incremented, what not is usually more complicated and
slower than doing the calculation over again.

Chrilly


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