> But, if you have a
>sufficiently parallel state representation, this could be done all in
>combinational logic and then pipelined at will to meet the clock.
I think this gets too complex and complicated.
My intention was/is a Cellular Automata like representation. Each
intersection knows just the states of the neighbour-intersections. This
would fit in a relative small FPGA (or one could place several cores in a
big one). But with this design counting e.g. liberties of a string or even
the length of a string is nasty. But it would e.g. be perfect for
calculating influence.
Note: One avoids usually in hardware incremental calculations. Marking what
has been already incremented, what not is usually more complicated and
slower than doing the calculation over again.
Yes, my thinking was right in line with cellular automata as well. There is
certainly some cool things you could do. But I did some reading on what the
internals of FPGAs are like and it just doesn't seem feasable because of all
the routing that would be needed. My experience is in ASIC design where you
have much more freedom. Too bad they are so expensive. I would love to
work a Go ASIC. What is the Powerball jackpot up to now?